1. Field of the Invention
The present invention relates to a synchronizing circuit for generating a reproduced clock signal synchronized with a reference clock signal and a clock data recovery circuit (hereinafter to be referred to as a CDR circuit) including the synchronizing circuit.
2. Description of the Related Art
Currently employed as a high-speed serial data communication scheme is an embedded clock scheme in which a clock signal is superimposed on data signals for transmission.
A receiver in a communication system that employs the embedded clock scheme is provided with a CDR circuit for acquiring a reproduced clock signal in phase with a data transition point from a received data signal with the help of the periodicity of data transition of the received data signal (for example, see FIG. 5 in Japanese Patent Application Laid-Open No. 2011-30058). The CDR circuit includes a phase locked loop (PLL) circuit which is made up of a phase/frequency detector, a charge pump, a loop filter, a voltage control oscillator, and a frequency divider (for example, see FIG. 5 in Japanese Patent Application Laid-Open No. 2011-30058).
However, in some cases, various factors would cause a false lock by which the frequency of a reproduced clock signal is locked to a frequency higher than a desired frequency, in the case of which it cannot be ensured to receive data with reliability.
In this context, such a CDR circuit is provided with a false-lock detection circuit for detecting whether there has occurred a false lock in the PLL circuit serving as the synchronizing circuit (for example, symbol 40 of FIG. 5 in Japanese Patent Application Laid-Open No. 2011-30058). This false-lock detection circuit detects whether there has occurred a false lock on the basis of the data train pattern that is obtained by sampling, at the timing of the reproduced clock signal mentioned above, a false-lock detection training pattern included in a received data signal. If a false lock is detected, then the false-lock detection circuit forcedly reduces the voltage supplied to a voltage control oscillator in the PLL circuit, thereby lowering the frequency of the reproduced clock signal that has been locked to a frequency higher than a desired frequency.
Furthermore, for example, external noise may cause a phase/frequency detector in the PLL circuit to malfunction, so that only those signals that are associated with a phase lead (or lag) continue to be supplied to a charge pump. This would cause the output from the charge pump to be fixed at a zero level. Thus, when a new data signal is received after that, the PLL circuit starts the initial synchronization with the output of the charge pump at the zero level. Thus, at this time, the synchronizing circuit having a feedback loop, such as the PLL circuit, may possibly be subjected to a false lock at a frequency different from a desired frequency.